Allied Telesis AR450S Manual de usuario descargar pdf (Pagina 38)

3-38 SHOW SWITCH COUNTER AR400 Series Router Software Reference

Software Release 2.6.6

C613-03079-00 REV A

Example To display the switching counters, use the command:

SHOW SWITCH COUNTER

Table 3-15: Parameters in the output of the SHOW SWITCH COUNTER

command .

Parameters Meaning

Packet DMA Counters

Receive

Counters for packets received.

Octets The number of octets received by the CPU from the switch chip.

Packets The number of packets received by the CPU from the switch chip.

Discards The number of packets received from the switch chip that were

discarded because either the receive queue was too long, or

because the free buffers in the router were below BufferLevel3, or

because there were no data bytes in the packet.

TooFewBuffers The number of packets received from the switch chip that were

discarded because the free buffers in the router were below

BufferLevel3.

NonOctetAlignedFrames The number of received frames with alignment and CRC errors.

FIFOOverruns The number of times reception of a packet failed because of a

FIFO overrun.

rameTooLongs The number of received packets that exceeded the maximum

permitted frame size.

FrameTooShorts The number of received packets that their lengths were less than

the minimum permitted frame size.

CRCErrors The number of received frames with CRC but not alignment

errors.

QueueLength The number of packets received from the switch chip waiting to

be processed by the CPU.

Transmit

Counters for packets transmitted.

Octets The number of octets transferred from the CPU to the switch

chip, including framing.

Packets The number of packets transferred from the CPU to the switch

chip.

Discards The number of packets waiting for transmission that were

discarded when the DMA process was reset due to an error.

Aborts The number of times the transmission of a packet was aborted

due to it taking excessive time for the transmission to complete.

DescriptorAreaFilleds The number of times the transmit descriptors are filled due to a

high rate of transfer of packets from the CPU to the switch chip.

FIFOUnderruns The number of times transmission of a packet failed because of a

FIFO underrun.

QueueLength The number of packets currently queued for transmission, or that

have been transmitted and are waiting to be purged from the

transmit queue.

General Counters

Resets The number of times the switch chip has been reset due to a

router configuration change.

1 2 ... 33 34 35 36 37 38 39 40 41 42 43 ... 47 48

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